Integrated circuits (ICs) form the basis for many electronic systems. An integrated circuit (IC) generally comprises a vast number of transistors and other circuit elements that are formed on a single semiconductor wafer or chip and are interconnected to implement a desired function. The complexity of these ICs requires the use of an ever increasing number of linked transistors and other circuit elements.
As IC technology progresses, there is a growing desire for a “system on a chip” in which the functionality of all of the IC devices of the system are packaged together without a conventional printed circuit board. In practice, however, it is very difficult to implement a truly high-performance “system-on-a-chip” due, in part, to process and structure limitations for pertinent logic and memory circuits.
As intermediate solutions between system-on-a-chip and more traditional independent chip integrations, various “system modules” have been introduced that electrically connect and package IC devices which are fabricated on the same or on different semiconductor wafers. Initially, system modules have been created by simply stacking two chips, e.g., a logic and memory chip, one on top of the other in an arrangement commonly referred to as chip-on-chip structure. The two chips may be electrically connected using wire bonding techniques. Subsequently, multi-chip module (MCM) technology has been utilized to stack a number of chips on a common substrate to reduce the overall size and weight of the package, which directly translates into reduced system size.
Existing MCM technology is known to provide performance enhancements over single chip or chip-on-chip (COC) packaging approaches for some applications. For example, when several semiconductor chips are mounted and interconnected on a common substrate through wire bonding, very small form factors may be achieved, which may lead to reduced weight and volume for an equivalent level of performance. However, MCM approaches still suffer from additional problems, such as bulky package and wire bonding that gives rise to stray inductances that significantly degrade the operation of the system module, make power distribution challenging, and may limit its use to lower power applications that require low communication bandwidth between the chips.
Advanced three-dimensional (3D) wafer-to-wafer vertical stack technology is being developed to realize more ideal “system on a chip” performance. In addition, it is expected to deliver a higher performance for the same power and chip size by reducing the length of the interconnects within the chip, which decreases the so called RC delays. Furthermore, 3D wafer-to-wafer bonding enables the integration of otherwise incompatible technologies. Early disclosures of related technologies include “Face To Face Wafer Bonding For 3D Chip Stack Fabrication To Shorten Wire Lengths” by J.F. McDonald et al., Rensselaer Polytechnic Institute presented on Jun. 27-29, 2000 VMIC Conference, and “Copper Wafer Bonding” by A. Fan et al., Massachusetts Institute of Technology, Electrochemical and Solid-State Letters, 2 (10) 534-536 (1999). In contrast to the existing MCM technology which seeks to stack multiple chips on a common substrate, 3-D wafer-to-wafer vertical stack technology involves vertically stacking many layers of active IC devices such as processors, programmable devices and memory devices inside a single chip to shorten average wire lengths, thereby reducing interconnect RC delay and increasing system performance.
One major challenge of 3-D wafer-to-wafer vertical stack integration technology is the bonding between wafers and between die in a single chip. In particular, a key challenge is ensuring that interfaced contact points do indeed form viable electronic contacts without gaps or shorts to adjacent contacts. FIGS. 1A-1D are useful for illustrating this challenge.
Referring to FIG. 1A, a contact substrate (100) comprising a substrate layer (102) and a series of contacts (105-108) opposes a second contact substrate (101) with similar contacts (109-112). As can be seen in the depicted illustration, the contacts do not protrude from the respective substrates by equal distances or “protrusion heights”. Referring to FIG. 1A, for example, is apparent that contact line 106 has a smaller protrusion height than contact 108. The amount of standard deviation from a mean protrusion height can be represented by the statistical value known as variance, which is well known convention. Since the contacts to be interfaced (105-112) do not have precisely equivalent protrusion heights, the grouping has a nonzero protrusion height variance. Such a scenario is quite typical in semiconductor processing due to systemic inaccuracies related to conventional processes such as chemical vapor deposition (CVP), physical vapor deposition (PVD), spin-on techniques, electroplating, and chemical mechanical planarization (CMP). To facilitate suitable electrical contact formation between pairings of contacts (105 and 109, 106 and 110, 107 and 111, 108 and 112, for example), compressive loading at elevated temperatures to facilitate diffusional creep may be employed.
Referring to FIG. 1B, the two contact substrates have been positioned opposite each other with substantially no compressive load, and it is apparent that, due to the nonzero contact protrusion variance, undesirable gaps (114, 115) are present. Referring to FIG. 1C, a substantially distributed compressive load (116) is applied to urge the first (100) and second (101) contact substrates toward each other. Given proper loading, materials selection and dimensioning, and temperature, diffusional creep, the migration of atoms from regions of higher stress to regions of lower stress by diffusion, may help to mitigate the gapping problem. As shown in FIG. 1D, atoms from the more highly compressively loaded contacts (105 and 109, 108 and 112, in FIGS. 1A and 1B) have migrated from the contact interface to lower stress regions, such as sidewalls of the contacts, to bridge (118) one of the regions of previous gapping (115), while the other gap (114) remains. The reliability with which contacts are properly interfaced has a significant effect upon the bandwidth of communication between active layers. Low reliabilities, for example, may directly translate into undesirably low bandwidths.
There is a need for optimized process and structure for controllably encouraging diffusional creep to facilitate desired contact patterns between devices.